The present invention relates to the field of integrated circuits technology, more particularly to phase-locked loops. Phase-locked loops (PLLs) are widely used in high performance digital systems. One application it is used is to multiply low frequency clock signals to high frequency clock signals with low jitter. With recent advances in the digital circuit technologies, more stringent performance requirements, including extremely low jitter, have been placed on PLLs. However, switching activities in digital system will introduce supply and substrate noises which will perturb the sensitive block in PLL. Any noise injected inside PLL contributes a source of jitter.
The loop bandwidth can be optimized according to the locking status to have a good control on the noise rejection from the input, power and ground, etc.
FIG. 1 shows the block diagrams of the general charge-pump phase-locked loop. Components 101, 102, 103, 104 and 105 are a phase frequency detector, charge-pump, loop filter, voltage controlled oscillator, and the feedback divider, respectively. CLKIN is provided to the first input of PFD 101. PFD provides a charging/discharging signal of UP/DN to CHPUP 102. The output of CHPUP is coupled to the loop filter 103 and to the VCO 104. The current from the CHPUP adjusts the frequency and the phase of VCO. The bias block generates the reference current, which is mostly used by the CHPUP. The output of the VCO is fed back to the input of the feedback divider 105. The output of the feedback divider is provided to the second input of PFD.
A charge-pump PLL is a negative feedback system. The phase and frequency difference between the two inputs to the PFD is near zero when PLL is in a steady state. Such a state is referred to “locked.” Otherwise, the state is “unlocked.”
Noise injection from the steady state leads to a transient response relating to the damping factor and the loop bandwidth of the loop system. Both the damping factor and the loop bandwidth have large effect on the loop stability, locking speed and the noise injection. The damping factor and loop bandwidth of the loop are function of physical quantities of the phase-frequency detector, the charge-pump current, the voltage-controlled oscillator gain and the feedback division value. Therefore the locking time is different under different settings.
Since the PLL is a second order system, there will be some overshoots and some undershoots in the transient response. These will worsen the jitter performance.
There are a number of different ways to detect the locked state of PLLs. According to one method, the maximum locking time is found. The maximum locking time generally is about 4 times the time constant of PLL. An off-chip stable capacitor is set so as to generate a delay that is substantially the same as the maximum locking time. Under another method, the clock cycle of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock is indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal is provided if said qualification counter exceeds a qualification threshold. U.S. Pat. No. 6,794,944, which is incorporated by reference, discloses such a method. In yet another method, the locked state is detected by cycling back and forth and searching for the occurrence of an unlocked condition when the PLL is locked, and searching for the occurrence of a locked condition when the PLL is unlocked. U.S. Pat. No. 6,762,631, which is incorporated by reference, discloses such a method.
Similar to the lock detection, there are a number of different ways to optimize the bandwidth. According to one method, the bandwidth is selected to be about 1/20 of the reference frequency. According to another method, self-Bias circuits that keep the ratio of the Wref (reference frequency) and Wb (loop bandwidth) constant and independent to the process. U.S. Pat. No. 6,329,882, which is incorporated by reference, discloses such a method. IN yet another method, two configurations are provided. The bandwidth is increased in the first configuration, and decreased in the second configuration. U.S. Pat. No. 6,504,437, which is incorporated by reference, discloses such a method.